Symmetric stacked fast binary counters based on reversible logic
نویسندگان
چکیده
منابع مشابه
Design of Low Power Counters Using Reversible Logic
ABSTRACT: In today’s world, the complexity of the chip is increasing as more and more devices are being connected on a single chip. Due to the high density of the chip, the power dissipation increases demanding better power optimization methods. One of the methods to achieve power optimization is by using reversible logic. It can be used in low power CMOS designs, quantum computing, nanotechnol...
متن کاملRegular Realization of Symmetric Reversible Logic Functions
Reversible logic is of growing importance to many future computer technologies. We introduce a regular structure to realize symmetric functions in binary reversible logic. This structure, called a 2 * 2 Net Structure, allows for more efficient realization of symmetric functions than the methods shown by previous authors. Our synthesis method allows to realize arbitrary symmetric function in a c...
متن کاملA Fast Symbolic Transformation Based Algorithm for Reversible Logic Synthesis
We present a more concise formulation of the transformation based synthesis approach for reversible logic synthesis, which is one of the most prominent explicit ancilla-free synthesis approaches. Based on this formulation we devise a symbolic variant of the approach that allows one to find a circuit in shorter time using less memory for the function representation. We present both a BDD based a...
متن کاملUltra-fast cell counters based on microtubular waveguides
We present a radio-frequency impedance-based biosensor embedded inside a semiconductor microtube for the in-flow detection of single cells. An impedance-matched tank circuit and a tight wrapping of the electrodes around the sensing region, which creates a close, leakage current-free contact between cells and electrodes, yields a high signal-to-noise ratio. We experimentally show a twofold impro...
متن کاملIn-Place Binary Counters
We introduce a binary counter that supports increments and decrements in O(1) worst-case time per operation. (We assume that arithmetic operations on an index variable that is stored in one computer word can be performed in O(1) time each.) To represent any integer in the range from 0 to 2−1, our counter uses an array of at most n bits plus few words of dlg(1 +n)e bits each. Extended-regular an...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: International Journal of Engineering & Technology
سال: 2018
ISSN: 2227-524X
DOI: 10.14419/ijet.v7i4.14141